A significant limiting factor in current n-channel MOSFETs is hot-electron-induced degradation, because of high channel electric fields and electron impact ionization rates in the micron and sub-micron n-channel devices. In hot electron injection, electrons are injected into the gate oxide by the high electric field created by the short channel region adjacent to the drain. As a result, the threshold voltage of the device is altered. In addition, overlap between the gate electrode and the source and drain results in parasitic capacitance between the diffusion region and the gate. This phenomenon, called Miller capacitance, decreases device speed.
"Lightly doped drain" (LDD) and "double diffused drain" (DDD) structures have been developed to minimize this degradation. Both of these structures are based on the theory that if there is a lightly doped n-surface layer adjacent to the channel, the peak electric field will be reduced and shifted from under the gate so that hot electron-induced degradation will be lessened. However, both pose other types of problems. Production of LDD structures requires the use of an additional mask to prevent LDD phosphorus from implanting into p-channel regions. In both the LDD and DDD structures one must construct a highly doped n+ region to produce low contact resistance at the n-channel source and drain for high-speed circuits.
The production of CMOS (complementary metal-oxide semiconductor) devices requires about eleven masks to produce the sequential layers of oxides, active areas and contacts which form the device. Each step in the device production generally involves a separate mask, except where "blanket" implant and oxidations can be effected. Each mask which must be used adds to the cost and time required to produce the device. Not only is expense incurred in the masking step itself, but the additional handling required for each mask step increases the possibility of defects, resulting in lower yields. The requirement of added mask steps to reduce hot electron effects has provided greater incentive to find other steps for which masks may be eliminated.
Prior research has been directed to techniques for eliminating masks whenever possible or to replace complex mask steps with simpler ones. One technique described involves a source/drain (S/D) counterdoping step to eliminate the S/D implant mask, in which a blanket implant of boron (p+) was followed by a masked phosphorus (n+) implant to counterdope the boron existing in the n+ source and drain regions. This, however, has required excessive quantities of phosphorus to be used to insure complete counterdoping of the boron.
It would therefore be advantageous to have a method for production of CMOS devices which would allow for elimination of masking steps while still providing a means of reducing hot-electron effects. It would also be advantageous for such method to permit elimination of an n+ layer without increasing the n-channel S/D contact resistance. It is to this end that the present invention is directed.